lecturer engineer iuliana chiuchisan
Laboratories
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Fundamentals of Digital Electronics & Digital Electronics
Undergraduated labs for 3rd year students from Mechatronics & labs for second year students from Electrotechnical Engineering Department.
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Digital Logic Systems
Undergraduated labs for first year students from Computer Science and Electronical Engineering Department.
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VLSI and HDL Design
Undergraduated labs for 4th year students from Computer Science and Electronical Engineering Department.
SEMESTER I
Proiectare Logica/ ANALIZA SI SINTEZA DISPOZITIVELOR NUMERICE/ CIRCUITE INTEGRATE DIGITALE 1(C, AIA, IETTI, anul 1)
Lab 1: Digital World
Lab 2: Boolean Algebra. Logic Gates
Lab 3: Logic Functions.Minimization using Veitch-Karnaugh diagrams
Lab 4: Analysis and synthesis of combinational logic circuits
Lab 5: Implementation of combinational circuits with decoders
Lab 6: Implementation of combinational circuits with multiplexer
Lab 7: Sequential digital design
Lab 8: Asynchronous and synchronous finite state machine
Lab 9: Digital 4-bit reversible counter
Lab 10: Digital 4-bit shift register
Annex 2: Integrated Circuits - Logic Gates.
Annex 3: Integrated Circuits - Combinational Circuits.
Annex 4: Integrated Circuits - Sequential Circuits.
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Lab 2: Instrumentație virtuală. Introducere în LabVIEW
Lab 3: Structuri in LabVIEW. Aplicatii
Lab 4: Prelucrarea imaginilor in LabVIEW
Lab 5: Prelucrarea semnalelor audio in LabVIEW
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Digital Electronics
Lab 2: Boolean Algebra. Logic Gates
Lab 3: Logic Functions. Veitch-Karnaugh diagrams
Lab 4: Analysis and synthesis of combinational logic circuits
Lab 5: Implementation of combinational logic circuits with multiplexer and with decoder
Annex 2: Integrated Circuits - Logic Gates
Annex 3: Integrated Circuits - Combinational Circuits
Annex 4: Integrated Circuits - Sequential Circuits
VLSI and HDL Design
Lab 2: Boolean Algebra. Logic Gates
Lab 3: Logic Functions.Minimization using Veitch-Karnaugh diagrams
Lab 4: Analysis and synthesis of combinational logic circuits
Lab 5: Implementation of combinational circuits with decoders
Lab 6: Implementation of combinational circuits with multiplexer
Lab 7: Sequential digital design
Lab 8: Asynchronous and synchronous finite state machine
Lab 9: Digital 4-bit reversible counter
Lab 10: Digital 4-bit shift register
Annexes
Annex 1: Codification.Annex 2: Integrated Circuits - Logic Gates.
Annex 3: Integrated Circuits - Combinational Circuits.
Annex 4: Integrated Circuits - Sequential Circuits.
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ACHIZITII DE DATE SI INSTRUMENTATII VIRTUALE (rcc, anul i)
Lab 1: Introducere, informaţie, semnal, achiziţii de date și sisteme de achiziții de date (SAD)Lab 2: Instrumentație virtuală. Introducere în LabVIEW
Lab 3: Structuri in LabVIEW. Aplicatii
Lab 4: Prelucrarea imaginilor in LabVIEW
Lab 5: Prelucrarea semnalelor audio in LabVIEW
SEMESTER II
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Digital Electronics
ELECTRONICA II / Electronica analogica si Digitala II/ electronica digitala (EN, SE, ESM, MCT, anul 2)
Lab 1: Introduction in Digital Systems.Lab 2: Boolean Algebra. Logic Gates
Lab 3: Logic Functions. Veitch-Karnaugh diagrams
Lab 4: Analysis and synthesis of combinational logic circuits
Lab 5: Implementation of combinational logic circuits with multiplexer and with decoder
Annexes
Annex 1: CodificationAnnex 2: Integrated Circuits - Logic Gates
Annex 3: Integrated Circuits - Combinational Circuits
Annex 4: Integrated Circuits - Sequential Circuits
VLSI and HDL Design
Proiectare VLSI (C, AIA, anul 4)
Intro:
Introduction in MODELSIM
Lab 1: Introduction. Structural design
Lab 2: Functional design in Verilog
Lab 3: Verilog procedural blocks
Lab 4: Describing combinational logic
Lab 5: Describing sequentiall logic
Lab 6: 4-bit counter design in Verilog
Lab 7: A RAM memory design in Verilog
Lab 8: A 8-level stack description in Verilog
Lab 9: RECAP
Lab 1: Introduction. Structural design
Lab 2: Functional design in Verilog
Lab 3: Verilog procedural blocks
Lab 4: Describing combinational logic
Lab 5: Describing sequentiall logic
Lab 6: 4-bit counter design in Verilog
Lab 7: A RAM memory design in Verilog
Lab 8: A 8-level stack description in Verilog
Lab 9: RECAP