Last projects (5 years)
1. Hardware CNN for digit recognition
Was implemented a simple neural network which recognize the digits. The weights and bias had been calculated on PC (training step). The weights and bias is memorized in ROM on Vivado Block Design. The test algorithm is implemented in two versions: HW-HLS and SW-MicroBlaze uP. The digits for recognition is memorized in RAM on Vivado Block Design, too. The project has had implemented on Arty development kit.
2. A Hardware RTOS implementing over a RISC V architecture
The aim of this project is to implement, test and validate the nHSE (Hardware Scheduler Engine for n tasks) technology as part of the nMPRA (Multi Pipeline Register Architecture - n degree of multiplication) microcontroller. This technology has been implemented using a 3-stage implementation RISCV pipeline processor. RISCV and nMPRA architecture was implemented using Vivado 2018.2 in Verilog HDL. nHSE and Debug module was implemented using Vivado HLS in SystemC. All RTL modules was tested on VC707 development kit.
3. ModBus for real-time systems implemented as a hardware Controller(ModBusE)
The aim of this project is to implement, test and validate the ModbusE technology. Basically it will create a hardware device (ModbusE Controller) which will implement all the functions ModbusE and Modbus.
4. PID implemenntation as a hardware block
In this project it was proposed to implement in hardware a PID command / control module of a DC motor. The command and control system as well as the description coefficients of a DC motor are implemented in the form of an IP block used in the development system in Vivado Block Design.
5. PID software algorithm implementation
Implementing PID software controller (python).
6. Real time data reading system from 10 video cameras of 5M each
This project aims to implement a hardware system that will read in real time the data from 10 video cameras of 5M each. The system is implemented on an PYNQ-Z2 board.
7. Real time RISCV architecture dual core with 8 threads
This project aims to implement a hardware architecture for a system that will contain two RISC V heterogenous cores, a multi pipeline registers system and a hardware instruction distribuitor for each CPU.. The system is implemented on an PYNQ-Z2 board.